This invention relates generally to analog-to-digital conversion systems and more particularly to analog-to-digital conversion systems adapted to convert a plurality of analog signals into corresponding digital signals, or words.
As is known in the art, analog-to-digital (ADCs) have a wide range of applications. In some applications, it is required that more than one analog signal be converted into a corresponding digital signal. One arrangement is shown in FIG. 1. In such an arrangement, the analog signals, here N analog signals, are fed to the input of a multiplexer (MUX). A control, or select, signal is fed to the multiplexer and the multiplexer couples one of the plurality of analog signals to an analog-to-digital converter (ADC) selectively in accordance with the control signal. The ADC produces a new conversion result at an update rate, or conversion period of T.sub.ADC seconds. However, after the multiplexer, in response to the control signal, changes from one input signal to another input signal, a number of conversion periods may be required before a valid, settled ADC result is produced, i.e., T.sub.SETTLE.gtoreq.T.sub.ADC, as indicated in FIG. 2.
A particular example of this is with a sigma-delta ADC featuring a second order sigma-delta modulator plus a third-order (sinc.sup.3) decimation filter. This particular ADC will not produce a valid result until a time period of T.sub.SETTLE =3*T.sub.ADC has elapsed because it takes the sinc.sup.3 filter 3 outputs update periods to settle (i.e., T.sub.SETTLE =3*T.sub.SINC3. In the case where this ADC is chopped, as described in U.S. Pat. No. 5,675,334, T.sub.SETTLE =2*T.sub.ADC. Thus, for a chopped ADC, T.sub.ADC =3*T.sub.SINC3, so that T.sub.SETTLE =6*T.sub.SINC3. If two independent inputs are to be converted with this chopped ADC, the time required will therefore be equal to 2*T.sub.SETTLE, i.e., 4*T.sub.ADC.
Another approach for converting more than one input analog signal is to use a separate ADC for each analog signal. For example, one such an arrangement is shown in FIG. 3 for two analog signals. Both ADCs convert simultaneously. Both ADCs are identical and are therefore capable of the same performance. That is, in the analog-to-digital conversion process, noise internal to the converter is generated. For example, with a switched capacitor sigma delta ADC, there is thermal noise generated. One way to increase the ADC's performance, more particularly, increase the resolution of the input signal in the presence of this thermally generated internal noise, is to increase the size of the capacitors used in the switching networks of the ADC. Increasing the size of the capacitors, however, increases the power required by the ADC and also increases the chip area required for the ADC. Another way to increase performance, here again by increasing the resolution of the input signal in the presence of this thermally generated internal noise is to increase the gain provided to the analog input signal. This, however, also requires an increase in the power required for the ADC. Thus, as the performance of an ADC is increased, the power and chip area required for the ADC generally increases. A third way to increase performance is to include a high impedance buffer for the ADC to reduce the loading effect of the ADC on the analog signal source. A fourth way the performance of an ADC may be improved is to increase the conversion rate of the ADC.
Thus, an increase in performance may be achieved by: increasing the resolution of the input signal in the presence of thermally generated noise and/or providing a high input impedance to the ADC and/or increasing the conversion rate of the ADC and/or increasing the gain of the ADC. Thus, if a first ADC has, relative to a second ADC, a higher resolution of the input signal in the presence of thermally generated noise and/or a higher input impedance to the ADC and/or a higher conversion rate and/or higher gain, the first ADC has, as defined herein, a higher degree of performance than the second ADC.